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| general description features ics9248-101 block diagram pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation frequency generator & integrated buffers for pentium/pro tm & k6 9248-101 rev c 2/29/00 pin configuration !" # "$ % & ! ' ()( *+$,-$." $ / ! 012#3 (4(567 *$." / !567 2#3 (8( *$." -+ - / ! ! 012#3 ((+)-)8 *$. (()8 *$. 9 (+(6#*$.")$8 $ !&&!& :; 0; 1 <$+,=">?(?$,= 48-pin ssop and tssop power groups .550 "@a50 b 01c+d?e" 012# .5556"@a556b567 01c d?e"567 2# .55 "@a5 b 01cfd?e" 012# .55)8"@a5)8b)8 "+) .556#"@a56#b6#"g"g+ .55 ;6b 00 ;6 h (6 +?1.55 :& & ! & ' ai' ! !&))?jg&.77 & $% ' ! & $ ii &!& ! !$ i 8j ?j$:& & ! i ! & !$:& !" & & !& & ! ! % % $ vddref ref0 gndref x1 x2 vddpci *cpu2.5_3.3#/pciclk_f *fs3/pciclk0 gndpci *sel24_48#/pciclk1 pciclk2 pciclk3 pciclk4 vddpci buffer in gndpci pciclk5 pciclk6 vddcor pci_stop# *pd# gnd48 s data sclk ref1/fs2* vddlcpu cpuclk_f cpuclk0 gndlcpu cpuclk1 cpuclk2 clk_stop# gndsdr sdram_f sdram0 sdram1 vddsdr sdram2 sdram3 gndsdr sdram4 sdram5 vddsdr sdram6 sdram7 vdd48 48mhz/fs0* 24_48mhz/fs1* ics9248-101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 { i c 2 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ics9248-101 pin descriptions ! " # !$ $ % && '(& " n i p r e b m u n e m a n n i pe p y tn o i t p i r c s e d 1f e r d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p l a t x , f e r 20 f e rt u o s d a o l s u b a s i r o f r e f f u b r e g n o r t s e h t s i t u p t u o f e r s i h t . k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 0 2# p o t s _ i c pn i ) 0 = e d o m , e d o m e l i b o m n i ( w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c ] 0 : 6 [ k l c i c p s t l a h , 6 1 , 9 , 3 4 4 , 0 4 , 3 3 d n gr w pd n u o r g 41 xn i k c a b d e e f d n a ) f p 6 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 52 xt u o. z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c 4 1 , 6i c p d d vr w pv 3 . 3 l a n i m o n , ] 0 : 6 [ k l c i c p d n a f _ k l c i c p r o f y l p p u s 7 # 3 . 3 _ 5 . 2 u p c 2 , 1 n i . t u p n i d e h c t a l . u p c v 3 . 3 = w o l , u p c v 5 . 2 = h g i h . v 3 . 3 r o 5 . 2 s i u p c l d d v r e h t e h w s e t a c i d n i f _ k l c i c pt u o . t n e m e g a n a m r e w o p r o f # p o t s _ i c p y b d e t c e f f a t o n k c o l c i c p g n i n n u r e e r f 8 3 s f 2 , 1 n i. t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 0 k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . t u p t u o k c o l c i c p 0 1 # 8 4 _ 4 2 l e s 2 , 1 n iz h m 8 4 = w o l n e h w z h m 8 4 r o 4 2 r e h t i e s t c e l e s 1 k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . t u p t u o k c o l c i c p , 3 1 , 7 1 , 8 1 , 1 1 , 2 1 ] 2 : 6 [ k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . s t u p t u o k c o l c i c p 5 1n i r e f f u bn i. s t u p t u o m a r d s r o f s r e f f u b t u o n a f o t t u p n i 9 1r o c d d vr w pv 3 . 3 . e r o c l l p e h t r o f n i p r e w o p 1 2# d p 1 n i e h t . e t a t s r e w o p w o l a o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i . s m 4 n a h t r e t a e r g e b t o n l l i w n w o d 2 28 4 d n gr w p. e r o c l l p d e x i f & s r e f f u b t u p t u o z h m 8 4 & 4 2 e h t r o f n i p d n u o r g , 2 3 , 1 3 , 9 2 , 8 2 8 3 , 7 3 , 5 3 , 4 3 ] 0 : 7 [ m a r d st u o . ) t e s p i h c y b d e l l o r t n o c ( n i p n i r e f f u b m o r f s t u p t u o r e f f u b t u o n a f , s t u p t u o k c o l c m a r d s 6 3 , 0 3r d s d d vr w p. v 3 . 3 l a n i m o n , e r o c l l p u p c d n a ] 0 : 7 [ m a r d s r o f y l p p u s 3 2a t a d sn ii r o f t u p n i a t a d 2 t u p n i t n a r e l o t v 5 , t u p n i l a i r e s c 4 2k l c sn ii f o t u p n i k c o l c 2 t u p n i t n a r e l o t v 5 , t u p n i c 5 2 z h m 8 4 _ 4 2t u o0 1 n i p y b e l b a t c e l e s k c o l c t u p t u o z h m 8 4 r o z h m 4 2 1 s f 2 , 1 n i. t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 6 2 z h m 8 4t u ok c o l c t u p t u o z h m 8 4 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 7 28 4 d d vr w p. e r o c l l p d e x i f d n a s r e f f u b t u p t u o z h m 8 4 & 4 2 r o f r e w o p 9 3f _ m a r d st u o# p o t s _ u p c y b d e t c e f f a t o n . t u p t u o k c o l c m a r d s g n i n n u r e e r f 1 4# p o t s _ k l cn i . w o l n e v i r d n e h w l e v e l " 0 " c i g o l t a ) 7 : 0 ( m a r d s & , ) 2 : 0 ( k l c u p c s t l a h t u p n i s u o n o r h c n y s a s i h t 5 4 , 3 4 , 2 4] 0 : 2 [ k l c u p ct u ou p c l d d v y b d e r e w o p , s t u p t u o k c o l c u p c 6 4f _ k l c u p ct u o# p o t s _ u p c e h t y b d e t c e f f a t o n . k c o l c u p c g n i n n u r e e r f 7 4u p c l d d vr w pv 5 . 2 s k c o l c u p c r o f y l p p u s 8 4 1 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 2 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f ics9248-101 $ :& '! %- %" $i'& & & % $ $ +$ :& i& '! ??1i - /3 $ :& !$. ! % $ )$ :&i 8i i$ ,$ : & '! "& k ! k & $:& ii & !&i &&i i &i $:& j& i%i"i& ! & i$:& $ f$ 7 (" ! "& $ general i 2 c serial interface information :& & & ! !$ # " ! ! $ how to write: /&3i $ /&3& 5+ ' /&3 ' /&3i ' /&3 ! i/j?3 &!&i, ' &i $ /&3i how to read: /&3 i $ /&3&5 ' ' & /&3' ! ' i /&3 ' !&i /&3 i controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write: ics9248-101 functionality . b$.<,=". b+$,.<,=$<,=":7b? ?l /g"g+3b)$88 3 s f2 s f1 s f0 s f u p c ) z h m ( i c p ) z h m ( 0000 0 0 . 4 2 13 3 . 1 4 0001 0 0 . 0 2 10 0 . 0 4 0010 9 9 . 4 1 13 3 . 8 3 0011 9 9 . 9 0 16 6 . 6 3 0100 0 0 . 5 0 10 0 . 5 3 0101 1 3 . 3 85 6 . 1 4 0110 0 0 . 7 3 15 2 . 4 3 0111 0 0 . 5 70 5 . 7 3 1000 0 0 . 0 0 13 3 . 3 3 100 1 0 0 . 5 97 6 . 1 3 10 10 1 3 . 3 87 7 . 7 2 10 11 3 3 . 3 3 13 3 . 3 3 1100 0 0 . 0 90 0 . 0 3 1101 2 2 . 6 97 0 . 2 3 1110 2 8 . 6 61 4 . 3 3 1111 5 . 1 95 . 0 3 " #$ " $ % " & ' ( ) * serial configuration command bitmap t i bn o i t p i r c s e dd w p 7 t i b d a e r p s r e t n e c , n o i t a l u d o m m u r t c e p s d a e r p s % 5 2 . 0 - 0 d a e r p s n w o d % 5 . 0 - o t 0 - 1 1 t i b ] 4 : 6 , 2 [ ] 4 : 6 , 2 [ t i b k l c u p c ) z h m ( k l c i c p ) z h m ( 1 e t o n 0 0 0 00 0 . 4 2 13 3 . 1 4 1 0 0 00 0 . 0 2 10 0 . 0 4 0 1 0 09 9 . 4 1 13 3 . 8 3 1 1 0 09 9 . 9 0 16 6 . 6 3 0 0 1 00 0 . 5 0 10 0 . 5 3 1 0 1 01 3 . 3 85 6 . 1 4 0 1 1 00 0 . 7 3 15 2 . 4 3 1 1 1 00 0 . 5 70 5 . 7 3 0 0 0 10 0 . 0 0 13 3 . 3 3 1 0 0 10 0 . 5 97 6 . 1 3 0 1 0 11 3 . 3 87 7 . 7 2 1 1 0 13 3 . 3 3 13 3 . 3 3 0 0 1 10 0 . 0 90 0 . 0 3 1 0 1 12 2 . 6 97 0 . 2 3 0 1 1 12 8 . 6 61 4 . 3 3 1 1 1 15 . 1 95 . 0 3 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 ] 4 : 6 , 2 [ t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0 & " " ) ! * + , -./ 0& 1 " # & 0! ) $ )2 ) $ $ * + + ics9248-101 , # $ %& 0;m i & !$ +$0&# /#n3 i % ! & $ " # - . / . & ' ) 0 1 )0 * t i b# n i pd w pn o i t p i r c s e d 7 t i b71 ) t c a n i / t c a ( f _ k l c i c p 6 t i b8 11 ) t c a n i / t c a ( 6 k l c i c p 5 t i b7 11 ) t c a n i / t c a ( 5 k l c i c p 4 t i b3 11 ) t c a n i / t c a ( 4 k l c i c p 3 t i b2 11 ) t c a n i / t c a ( 3 k l c i c p 2 t i b1 11 ) t c a n i / t c a ( 2 k l c i c p 1 t i b0 11 ) t c a n i / t c a ( 1 k l c i c p 0 t i b81 ) t c a n i / t c a ( 0 k l c i c p " # 21- . / . & ' ) 0 1 )0 * t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b6 41 ) t c a n i / t c a ( f _ k l c u p c 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b9 31 ) t c a n i / t c a ( f _ m a r d s 2 t i b2 41 ) t c a n i / t c a ( 2 k l c u p c 1 t i b3 41 ) t c a n i / t c a ( 1 k l c u p c 0 t i b5 41 ) t c a n i / t c a ( 0 k l c u p c " #3 -4- . / . & ' ) 0 1 )0 * t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b8 21 ) e v i t c a n i / e v i t c a ( 7 m a r d s 2 t i b9 21 ) e v i t c a n i / e v i t c a ( 6 m a r d s 1 t i b1 31 ) e v i t c a n i / e v i t c a ( 5 m a r d s 0 t i b2 31 ) e v i t c a n i / e v i t c a ( 4 m a r d s 5 ics9248-101 " # . - . / . & ' ) 0 1 )0 * " +# 6 - . / . & ' ) 0 1 )0 * , # $ %& 0;m i & !$ +$0&# /#n3 i % ! & $ t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 # ) 8 4 _ 4 2 l e s ( 4 t i b-1 ) d e v r e s e r ( 3 t i b-x # 1 s f d e h c t a l 2 t i b-1 ) d e v r e s e r ( 1 t i b-x # 3 s f d e h c t a l 0 t i b-1 ) d e v r e s e r ( t i b# n i pd w pn o i t p i r c s e d 7 t i b4 31 ) t c a n i / t c a ( 3 m a r d s 6 t i b5 31 ) t c a n i / t c a ( 2 m a r d s 5 t i b7 31 ) t c a n i / t c a ( 1 m a r d s 4 t i b8 31 ) t c a n i / t c a ( 0 m a r d s 3 t i b6 21 ) t c a n i / t c a ( z h m 8 4 2 t i b5 21 ) t c a n i / t c a ( z h m 4 2 1 t i b8 41 ) t c a n i / t c a ( 1 f e r 0 t i b21 ) t c a n i / t c a ( 0 f e r 7 ics9248-101 clk_stop# timing diagram 012:; n & & '& $ & ' $ 012:; n & i& $:& && ' i / 012:; n& !& 3 ?? '$7 & ' & & ' i $:& ' i &&!&& !& & $ ' & ) ' ' &) '$ 3 $ ! 4 # 5 46789: ; +! $) $+ < 9! +!= ! 4 # 5 ! 48>.? 8&3@ a )+ )+ ! 48>.? 46789: ; 8&3@ ,2/ !" . 3 ! 5 ) pciclk [6:0] sdram [7:0] cpuclk [2:0] cpuclk _f sdram_f pci_stop# (high) clk_stop# internal cpuclk ics9248-101 pd# timing diagram :& & % & ! & &$ 5n & % $:& ! i& &% ! & ' & $ ' ! &% $m& 5n % 'i % % & ! &. ; $:& i &)$:& & i& i i !& & i $ 2:; n 012:; n io !& $:&6#)8 '9i &0;m i $5& & ! " !& !&6# ' & 0;m & ' $ 3 $ ! 4 #46 b ! 48>.? c 3 !" ! 8 6" ! < &; " &; +! $) $+ < 9! +!= ! . 9! ! ! 4: ! 4+ 5 d & $ !" "! @%= 8$ "! 4 # @%= cpuclk pciclk vco crystal pd# ics9248-101 pci_stop# timing diagram 2:; n & & $ & 01cfd?e ' $ 2:; n & i& $:& && 01cfd?e 'i / 2:; n& !& 3 ? 01cfd?e '$ 01cfd?e ' & & !& &!$ 01cfd?e ' & ! 01 '" 01 '$ 3 $ ! 4 #46 b ! 48>.? c 4789: ; +! $) $+ < 9! * ) +!= ! 48>.? 3 ! 5 ) . 46789: ; !" ! ! b c cpuclk (internal) pciclk_f (internal) pciclk_f (free-running) clk_stop# pciclk [6:0] pci_stop# ics9248-101 shared pin operation - input/output pins fig. 1 :&-; !i/ -3& % ! & % $ 5 ! (" & $ :& ! % /% !3& & & )(i &$7& (; "/7 & !% 3"&% &!& & $& & & i '9 $ :!/ 3& ! ! & " & & .55 / ! 3 &@a5/ ! ?3% ! $7? 1 &/?13 % i&& ; ! ! % ! ! & ( ! ! % ! & ' !&i ! $ # !$+& & ! & $# !$ & & &i/ % !3 !&% p ! $# !$+i% ! ! & & i & q &i$ :& ! & j & $ :& ! & ! & % && & ' ! $:& &%i % & ' ! i " &!&&! ! /3$ ics9248-101 fig. 2a fig. 2b ics9248-101 absolute maximum ratings . ! $$$$$$$$$$$$$$$$$$$$$$$$$$$ $?. 0! $$$$$$$$$$$$$$$$$$$$$$$$$$$$$ @a5r?$,.. s?$,. 7i ; !: $$$$$$$$$$$$ ?l s ?l : $$$$$$$$$$$$$$$$$$$$$$$$ ,l !: $$$$$$$$$$$$$$$$$$$$$$ rf,l s,?l i%& !&% $:& ! &% && i%& & & $9i 9 ! 9 i $ electrical characteristics - input/supply/com mon output param eters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v c l = 0 pf; select @ 66mhz 90 150 c l = 0 pf; select @ 100mhz 120 170 c l = 0 pf; select @ 133mhz 151 180 powerdown current i ddpd cl = 0 pf; input address vdd or gnd 250 600 a input frequency f i v dd = 3.3 v 12 14.318 16 m hz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf clk stab ilizatio n 1 t stab from v dd = 3.3 v to 1% target freq. 5.5 ms skew 1 t cp u-p ci1 v t = 1.5 v 12.8 4 ns 1 guaranteed by des ign, not 100% tes ted in production. ma operating supply current i dd3.3 op electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units c l = 0 pf; select @ 66.8 m hz 8 15 c l = 0 pf; select @ 100 m hz 11 18 c l = 0 pf; select @ 133 m hz 17 20 powerdown current i ddlpd cl = 0 p f; in p ut address vdd or gnd <1 10 a skew 1 t cpu-pci2 v t = 1.5 v; v tl = 1.25 v 12.44 ns 1 guaranteed by design, not 100% tested in production. i ddl2.5 operating supplycurrent ma ics9248-101 electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output high voltage v oh2a i oh = -20 ma 2.4 2.85 v output low voltage v ol2a i ol = 12 ma 0.31 0.4 v output high current i oh2a v oh = 2.0 v -45 -27 ma output low current i ol2a v ol = 0.8 v 22 29 ma rise time 1 t r2a v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time 1 t f2a v oh = 2.4 v, v ol = 0.4 v 1.4 2 ns duty cycle 1 d t2a v t = 1.5 v 45 55 % skew window 1 t sk2a v t = 1.5 v 80 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2a v t = 1.5 v 200 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 20 pf parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12 ma 2 2.3 v output low voltage v ol2b i ol = 12 ma 0.31 0.4 v output high current i oh2b v oh = 1.7 v -39 -21 ma output low current i ol2b v ol = 0.7 v 22 26 ma rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 1.3 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 1.4 1.6 ns v t = 1.25 v, < 133 mhz 45 47.5 55 v t = 1.25 v, >= 133 mhz 42 47 52 skew window 1 t sk2b v t = 1.25 v 70 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 200 300 ps 1 guaranteed by design, not 100% tested in production. % d t2b duty cycle 1 ics9248-101 electrical characteristics - pci t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -18 ma 2.4 3 v output low voltage v ol1 i ol = 9.4 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -62 -33 ma output low current i ol1 v ol = 0.8 v 38 43 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.5 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew window 1 t sk1 v t = 1.5 v 180 500 ps jitter, one sigma 1 t j 1s1 v t = 1.5 v 15 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -250 75 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh3 i oh = -28 ma 2.4 3 v output low voltage v ol3 i ol = 19 ma 0.3 0.4 v output high current i oh3 v oh = 2.0 v -69 -46 ma output low current i ol3 v ol = 0.8 v 32 42 ma rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 11.3ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 1.3 2 ns duty cycle 1 d t3 v t = 1.5 v 45 50 55 % skew window 1 t sk3 v t = 1.5 v 185 250 ps propagation time 1 (buffer in to output) t sk3 v t = 1.5 v 45ns 1 guaranteed by design, not 100% tested in production. + ics9248-101 electrical characteristics - 24,48mhz, ref(0:1) t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -14 ma 2.4 2.6 v output low voltage v ol5 i ol = 6 ma 0.22 0.4 v output high current i oh5 v oh = 2.0 v -32 -20 ma output low current i ol5 v ol = 0.8 v 16 22 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 2 4 ns duty cycle 1 d t5 v t = 1.5 v 45 1 55 % jitter, one sigma 1 t j 1s5 v t = 1.5 v 150 250 ps jitter, absolute 1 t jabs5 v t = 1.5 v -600 600 ps 1 guaranteed by design, not 100% tested in production. 5 ics9248-101 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9248 y f-101-t !" a188: . 3 & / &&% 3 # !" $ % 48 3 1 8 & 9 d ics xxxx y f - ppp - t 7 ics9248-101 ordering information ics9248 y g-101-t !" '1988: . 3 & / &&% 3 # !" $ % 48 3 1 8 & 9 d ics xxxx y g - ppp - t |
Price & Availability of ICS9248YG-101LF-T
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